The present invention relates to a method and an apparatus for classifying a defect on a semiconductor wafer.
Generally, in a process for fabricating an integrated circuit on a semiconductor wafer, it is known that the attachment of dust carried into a clean room and particles produced in an apparatus for fabricating the integrated circuit to the semiconductor wafer can have a disastrous effect on a yield and product quality. Besides the dust and the particles produced in the apparatus, an abnormal region created on the semiconductor wafer by implementing the production process without eliminating the dust and the particles can be included as a factor which renders a bad effect. Hereafter, all factors which bring about a reduced yield and a reduced product quality are referred to as "defects" in order to simplify the description.
In order to reduce such defects, it has been desired that the type of the defect be distinguished and that a suitable operation be adapted to prevent an occurrence of the defect in the production process where the defect has occurred. Known apparatuses for classifying a defect on a semiconductor wafer include, for example, an apparatus A0 disclosed in Japanese Examined Patent Publication
FIG. 1 is a block diagram of the defect classifying apparatus A0, and FIG. 2 is a diagram showing the operation of the apparatus A0 of FIG. 1. As shown in FIG. 1, the apparatus A0 is provided with a camera 52 for picking up an image of the surface of a semiconductor wafer 51 as an object to be inspected. The camera 52 is electrically connected with an analog-to-digital (A/D) converter 53. A surface image I of the semiconductor wafer 51 picked up by the camera 52 (hereinafter, "inspection image") is converted into a digital signal, and is inputted into a comparator 54b of a defect region extraction circuit 54. In this manner, multi-gradation image data of the inspection image (hereinafter, "inspection image data") is fed to the comparator 54b.
The defect region extraction circuit 54 includes an image memory 54a in which multi-gradation image data (hereinafter, "reference image data") corresponding to a surface image I0 (hereinafter, "reference image") of a semiconductor wafer having no defect is stored in advance. The reference image data is fed from the image memory 54a to the comparator 54b. When the reference image data and the inspection image data are input to the comparator 54b in this way, both image data are compared pixel by pixel to generate defect region extraction data (binary image data) in which "1" denotes a defect region and "0" denotes a region other than the defect region. The defect region extraction data is fed to a geometric feature extraction circuit 55. It should be noted that B1 in FIG. 2 identifies a defect region extraction image obtained based on the defect region extraction data.
The circuit 55 includes an image memory 55a for temporarily storing the defect region extraction data, an image memory 55b for storing pattern data, and a computer 55c. The "pattern data" is such that the reference image is divided into a plurality of wiring partial regions R (FIG. 2) which are coded so as to be distinguishable from each other. In this example, the wiring partial regions are classified into three patterns: "0", "1", and "2". The computer 55c reads the defect region extraction data from the image memory 55a and the pattern data from the image memory 55b, and compares both read data, thereby calculating areas S0, S1, S2 taken up by the respective patterns "0", "1", and "2" within the defect region (a hatched region in the defect region extraction image BI) as feature parameters concerning the defect region and feeding them to a defect classification computer 56.
The computer 56 classifies the defect based on the feature parameters obtained as above. In other words, the computer determines whether the wiring has peaking, lacking or fault defects in the defect region by comparing the areas S0, S1, S2 with each other.
As described above, the prior art defect classifying apparatus A0 classifies the defect based on the defect region extraction data (binary image data). In this respect, the defect classifying method adopted by this apparatus A0 can be said to be a defect classifying method which bases only the geometric information such as the area, width and peripheral length of the defect. In other words, the apparatus A0 can only determine the type of the defect as the pecking, lacking and fault of the wiring, but cannot detect in which production process the defect has occurred. Accordingly, with the prior art apparatus A0, it is impossible to specify the production process where the defect has occurred and to improve this production process.
Further, since the pattern data are stored in the image memory in advance, all pattern data of the partial regions used for the defect classification need to be stored. As a result, the image memory 55b is disadvantageously required to have a huge memory capacity.